1. Field of the Invention
The present invention relates to a photoelectric conversion apparatus and an image pickup system.
2. Description of the Related Art
It is known that an analog-to-digital (AD) converter is provided for each column of a pixel array in a solid-state image pickup apparatus. Japanese Patent Laid-Open No. 2009-10787 describes a configuration in which a signal holding switch and a signal holding capacitance directly connected to the AD converter are provided upstream of the AD converter provided in each column of the pixel array. According to Japanese Patent Laid-Open No. 2009-10787, a read operation for an analog signal from a pixel, and an AD conversion operation thereof are performed in parallel by turning off the signal holding switch during an AD conversion period for the analog signal held in the signal holding switch, so that high-speed reading can be realized.
However, the configuration described in Japanese Patent Laid-Open No. 2009-10787 could cause a fixed pattern noise for each column. A reason for this noise generation will be described below.
FIG. 13 is a diagram taken from FIG. 8 of Japanese Patent Laid-Open No. 2009-10787 and illustrates a circuit configuration of a voltage comparison unit 252 included in the AD conversion unit. In this circuit, when a relationship of magnitude between a “pixel signal” and a “RAMP” corresponding to input signals to the voltage comparison unit 252 is reversed (in other words when the “pixel signal” being smaller than “RAMP” changes to become greater than “RAMP” as “RAMP” decreases with time), a voltage at a drain of a transistor 314 corresponding to an output of the voltage comparison unit 252 is changed from a high level to a low level or from the low level to the high level. This change also affects a gate of the transistor 314 via a gate-drain capacitance of the transistor 314. Further, since a gate and a drain of the transistor 312 are connected to the gate of the transistor 314, the change caused in the drain of the transistor 314 also affects the gate and the drain of the transistor 312. Furthermore, since the drain of the transistor 312 is connected to a drain of a transistor 302 that is an input transistor of the voltage comparison unit 252, the change caused in the drain of the transistor 312 also affects a gate of the transistor 302. Accordingly, a phenomenon in which an output of the voltage comparison unit 252 affects the “pixel signal” corresponding to an input of voltage occurs.
According to the configuration described in Japanese Patent Laid-Open No. 2009-10787, the “pixel signal” is directly connected to the signal holding capacitance and is electrically disconnected from a unit pixel during the AD conversion period. Accordingly, a transient change of a drain voltage of the transistor 314 which is caused during the AD conversion period also changes a signal voltage of the signal held in the signal holding capacitance. That is, since the signal voltage of the signal held in the signal holding capacitance may be a voltage different from the voltage originally held, a value of digital data obtained as a result of the AD conversion may be an inaccurate value. In addition, an influence imposed on the “pixel signal” by the change of the drain voltage of the transistor 314 varies for each column because of variations in manufacturing the voltage comparison units 252, and this becomes fixed pattern noise for each column.